The present invention relates to a synchronous DRAM(SDRAM) and a method for data accesses of an SDRAM.
In recent years, the progress of bandwidth of a DRAM (dynamic random access memory) has been preceded by the progress in speed of MPU (micro-processing unit), thus this has caused serious limitation on the improvement of the system performance. In a DRAM, reading and writing data is executed by specifying a row address and a column address among memory cells normally disposed in a matrix form. When a row address whose memory cell to be accessed has been specified, regardless of its column address, all the data in the specified row address are amplified by sense amplifiers. In succession, when a column address has been specified, the data corresponding to the specified column address are output among the data amplified by the sense amplifiers. A summary of data-read timing is generally illustrated in FIG. 7(a).
Further, when a row address has been specified, since all the data are amplified by sense amplifiers, in case of read data of the same row address in succession, the objective data have already been read by the sense amplifiers. Accordingly, in case of read data of the same row address in succession, specification of only a column address will suffice. A summary of data-read timing in this case can generally be understood as shown in FIG. 7(b). In the page mode for continuous data accesses of the same row, since it is not necessary to respecify the row address, data can be read out at higher speed than a conventional method shown in FIG. 7(a).
Likewise, a synchronous DRAM (SDRAM) has extensively been introduced for practical use. In an SDRAM, when a row address and a column address of the initial data have been specified, following addresses are automatically generated inside of a memory chip to generate data to be output in succession synchronous with the clock. A summary of data-read timing in this case is illustrated in FIG. 8. The number of data (burst length) output in succession can be selected by an optional number such as 2, 4, or 8. In the burst mode for data accesses synchronous with the clock, since data are accessible per clock, data can be read out at higher speed than the page mode shown in FIG. 7(b).
However, except for the data-output synchronous with clock, basically, the burst mode is similar to the conventional page mode, in which high-speed access is realized by specifying a column address against a number of sense amplifiers activated by a single row address. Accordingly, in the access against the same row address, reading speed is greatly improved. However, when accessing a different row address, data must newly be read into sense amplifiers, and thus, reading speed is not improved.
In order to improve the speed of accessing a different row address, each SDRAM comprises a plurality of memory banks. Each of the memory banks can function itself almost like an independent DRAM. It is so arranged that a decrease of the access speed can be curbed by activating or precharging other banks while accessing a bank.
However, in the above method, unless the burst length is long enough, latent time is generated in the access between banks to fail to become seamless like the case of accessing against a column of the same row. For example, in the case of such an SDRAM comprising 16 Mbit, 100 MHz, 3 of CAS (column address strobe) latencies, and 2 of banks (bank 1/bank 2), as shown in FIG. 9, when the burst length is rated to be 4, latency time corresponding to 3 clocks is generated in the course of accessing a different bank to cause the substantial data-transmission rate to be decreased to 73%(8/11) of the clock frequency. As a matter of course, when using a number of banks by increasing their number, basically, a seamless access can be realized.
Nevertheless, when the number of banks has been increased, it is necessary to provide a number of row-and-column access commands and row-precharge commands. For example, if the number of banks of 4-bit- burst shown in FIG. 9 is increased to 4 (bank 0xcx9cbank 3), latency time on the data bus is decreased. However, in the course of accessing bank 2 following bank 0 and bank 1, the timing of the row-address specifying command overlaps that of the precharge command of bank 0 to cause an access to bank 3 to be held awaiting by 1 clock. Further, because of the relationship between the command for specifying a column address of bank 2 and the precharge command of bank 1, as shown in FIG. 10, vacancy corresponding to 2 clocks is eventually generated to result in the failure to achieve a seamless access. when using a number of banks and short-length burst, a clock slot for sequentially accommodating all the commands is lost, which results in the failure to materialize the seamless access.
The object of the invention is to eliminate the latency time for a read/write of data generated when the burst-length is short whereby makes it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks to enable the band-width of SDRAM to approximate the data transmission rate at the peak moment determined by the maximum frequency of the clock.
The essential of the SDRAM in the present invention is that the SDRAM comprises a bank-specifying means for specifying a bank to be accessed, an address-specifying means for specifying an address of data to be accessed inside said bank to be accessed, a bank-changing means for varying a bank specified by the said bank-specifying means as per predetermined sequence, and an address-changing means for varying addresses specified by said address-specifying means across a predetermined number of data.
The essential of the method for accessing data of the SDRAM of the invention is that the method comprises a step of specifying a bank to be accessed, a step of specifying an address of data to be accessed inside of said accessible bank, a step of accessing said specified bank as per predetermined sequence, and a step of accessing data of said specified address inside said specified bank across a predetermined number of data.
In the SDRAM of the invention, an address inside of the same bank is increased across a burst-length portion. After the address of the initial bank has been increased by the burst-length portion, the sequence is shifted to the following bank to cause the address inside the bank to be increased across the burst-length portion. After completing access to the last bank, the access returns to the initial bank to cause the address inside the bank to be accessed from the continual portion of the address accessed in the last round. When completing the access to the bank, the bank is automatically precharged.